{"id":881,"date":"2019-10-23T15:57:30","date_gmt":"2019-10-23T07:57:30","guid":{"rendered":"http:\/\/149.129.74.185\/?p=881"},"modified":"2019-10-23T15:57:30","modified_gmt":"2019-10-23T07:57:30","slug":"%e8%ae%a1%e7%ae%97%e6%9c%ba%e4%bd%93%e7%b3%bb%e7%bb%93%e6%9e%84-week-6-note","status":"publish","type":"post","link":"http:\/\/www.magicmipamipa.com\/?p=881","title":{"rendered":"[\u8ba1\u7b97\u673a\u4f53\u7cfb\u7ed3\u6784] Week 6 Note"},"content":{"rendered":"
<\/div>\n
Describe data hazard and how to solve the hazard\uff1a<\/div>\n
\u6570\u636e\u7ade\u4e89\u7684\u51e0\u79cd\u7c7b\u578b\u548c\u89e3\u51b3\u65b9\u6848\uff1b<\/div>\n
<\/div>\n
1\u3002forwarding<\/div>\n
add R1\uff0cR0\uff0cR0<\/div>\n
sub R3\uff0cR1\uff0cR2<\/div>\n
<\/div>\n
2\u3002stall<\/div>\n
add R1\uff0cR0\uff0cR0<\/div>\n
add R2\uff0cR3\uff0cR3<\/div>\n
sub R4\uff0cR1\uff0cR5<\/div>\n
<\/div>\n
3\u3002 forwarding<\/div>\n
lw R0\uff0c0\uff08R1\uff09 MEM\/WB<\/div>\n
sw R0\uff0c0\uff08R2\uff09EXE<\/div>\n
<\/div>\n
4\u3002forwarding<\/div>\n
add R1\uff0cR0\uff0cR0<\/div>\n
add R4\uff0cR5\uff0cR5<\/div>\n
add R6\uff0cR7\uff0cR6<\/div>\n
add R2\uff0cR1\uff0cR1<\/div>\n
<\/div>\n
5\u3002stall+forwaring<\/div>\n
lw R1\uff0c0\uff08R2\uff09\u00a0 MEM\/WB<\/div>\n
add R3\uff0cR1\uff0cR4 ID<\/div>\n
\n
\n<\/div>\n
5 stage pipeline\u00a0\u4e94\u7ea7\u6d41\u6c34\u7ebf\u7684\u4e94\u4e2a\u72b6\u6001\uff1a\u00a0<\/strong><\/div>\n
\n
    \n
  • IF (Instruction fetch cycle)\n
      \n
    • IR\u2190Mem[PC];<\/li>\n
    • NPC\u2190PC=PC+4;<\/li>\n<\/ul>\n<\/li>\n
    • ID (Instruction decode\/register fetch cycle)\n
        \n
      • A\u2190Regs[rs];<\/li>\n
      • B\u2190Regs[rt];<\/li>\n
      • Imm\u2190sign-extended immediate field of IR;<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
        \n
        \n
        The first two stages of MIPS pipeline do the same functions for all kinds of instructions.<\/em><\/div>\n<\/blockquote>\n
          \n
        • EX (Execution\/effective address cycle)\n
            \n
          • Memory reference:\n
              \n
            • ALUoutput\u2190A+Imm<\/li>\n<\/ul>\n<\/li>\n
            • Register-Register ALU instruction:\n
                \n
              • ALUoutput\u2190A func B;<\/li>\n<\/ul>\n<\/li>\n
              • Register-Immediate ALU instruction:\n
                  \n
                • ALUoutput\u2190A op Imm;<\/li>\n<\/ul>\n<\/li>\n
                • Branch:\n
                    \n
                  • ALUoutput\u2190NPC+(Imm <<2 );<\/li>\n
                  • Cond\u2190(A==0))<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n
                  • MEM(Memory acces\/branch completion cycle)\n
                      \n
                    • Memory reference:\n
                        \n
                      • LMD\u2190Mem[ALUoutput] or<\/li>\n
                      • Mem[ALUoutput]\u2190B<\/li>\n<\/ul>\n<\/li>\n
                      • Branch:\n
                          \n
                        • If (cond) PC\u2190ALUoutput<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n
                        • WB (Write back cycle)\n
                            \n
                          • Register-Register ALU instruction\n
                              \n
                            • Regs[rd]\u2190ALUoutput;<\/li>\n<\/ul>\n<\/li>\n
                            • Register-Immediate ALU instruction\n
                                \n
                              • Regs[rt]\u2190ALUoutput;<\/li>\n<\/ul>\n<\/li>\n
                              • Load Instruction:\n
                                  \n
                                • Regs[rt]\u2190LMD;<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/div>\n<\/div>\n

                                   <\/p>\n

                                  A hazard is a condition that prevents an instruction in the pipe from executing its next scheduled pipe stage<\/p>\n

                                  \u3010\u7ade\u4e89\/\u5192\u9669\uff1a\u963b\u6b62\u4e00\u6761\u6307\u4ee4\u8fdb\u884c\u4e0b\u4e00\u6b65\u72b6\u6001\u7684\u60c5\u51b5\u3011<\/p>\n

                                  Taxonomy of Hazards \u4e09\u79cd\u7ade\u4e89\/\u5192\u9669\uff1a<\/p>\n

                                  1.Structural hazards \u7ed3\u6784\u5316\u7ade\u4e89\u3010\u4e94\u7ea7\u6d41\u6c34\u7ebf\u7684ALU\u662f\u4e0d\u4f1a\u5f15\u8d77\u7ed3\u6784\u7ade\u4e89\u7684\u3011<\/div>\n

                                  These are conflicts over hardware resources<\/span>.\u786c\u4ef6\u51b2\u7a81<\/strong><\/p>\n

                                  \n
                                  OK, maybe (1)add extra hardware resources<\/span><\/strong>;<\/em><\/div>\n
                                  or full pipelined the functional units((2)split duble bump<\/span><\/strong>);<\/em><\/div>\n
                                  otherwise still have to (3)stall<\/span><\/strong><\/em><\/div>\n<\/blockquote>\n
                                  2.Data hazards \u6570\u636e\u7ade\u4e89<\/div>\n
                                  Instruction depends on result of prior computation which is not ready (computed or stored) yet<\/div>\n
                                  \u6307\u4ee4\u95f4\u5b58\u5728\u6570\u636e\u76f8\u5173\u6216\u540d\u79f0\u76f8\u5173\uff0c\u800c\u4e14\u5b83\u4eec\u975e\u5e38\u63a5\u8fd1\uff0c\u8db3\u4ee5\u4f7f\u6267\u884c\u671f\u95f4\u7684\u91cd\u53e0\u6539\u53d8\u5bf9\u76f8\u5173\u64cd\u4f5c\u6570\u7684\u8bbf\u95ee\u987a\u5e8f\u3002<\/div>\n
                                  \n
                                  OK, we did these, (1)Double Bump<\/span><\/strong>, (2)Forwarding path<\/span><\/strong>,<\/em><\/div>\n
                                  (3)software scheduling<\/strong><\/span>, otherwise have to (4)stall<\/span><\/strong><\/em><\/div>\n<\/blockquote>\n
                                  \u00a03.Control hazards \u63a7\u5236\u7ade\u4e89<\/div>\n
                                  branch condition and the branch PC are not available in time to fetch an instruction on the next clock<\/div>\n
                                  \u5206\u652f\u65e0\u6cd5\u53ca\u65f6\u83b7\u5f97\u4e0b\u4e00\u65f6\u949f\u7684\u6307\u4ee4\u3002<\/div>\n

                                  Control hazard \u63a7\u5236\u7ade\u4e89\u7684\u56db\u79cd\u89e3\u51b3\u65b9\u6848\uff1a<\/p>\n

                                    \n
                                  • Freeze or flush the pipeline \u51bb\u7ed3\u6216\u5237\u65b0\u6d41\u6c34\u7ebf<\/li>\n
                                  • Predict-not-taken (Predict-untaken) \u9884\u6d4b\u4e0d\u8f6c\u79fb\n
                                      \n
                                    • Treat every branch as not taken<\/li>\n
                                    • \n
                                      \u9884\u6d4b\u547d<\/span><\/em>\u4e2d\u6709\u597d\u5904\uff0c<\/em>\u9884\u6d4b\u4e0d\u547d\u4e2d\u65f6\u67093\u4e2a\u505c\u987f<\/em><\/div>\n<\/li>\n<\/ul>\n<\/li>\n
                                    • Predict-taken \u9884\u6d4b\u8f6c\u79fb\n
                                        \n
                                      • Treat every branch as taken<\/li>\n<\/ul>\n<\/li>\n
                                      • Delayed branch \u5ef6\u65f6\u5206\u652f<\/li>\n<\/ul>\n

                                         <\/p>\n","protected":false},"excerpt":{"rendered":"

                                        Describe data hazard and how to solve the hazard\uff1a […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[21,16],"tags":[],"_links":{"self":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts\/881"}],"collection":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=881"}],"version-history":[{"count":1,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts\/881\/revisions"}],"predecessor-version":[{"id":882,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts\/881\/revisions\/882"}],"wp:attachment":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=881"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=881"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=881"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}