{"id":1117,"date":"2019-12-18T13:52:31","date_gmt":"2019-12-18T05:52:31","guid":{"rendered":"http:\/\/149.129.74.185\/?p=1117"},"modified":"2019-12-18T15:43:34","modified_gmt":"2019-12-18T07:43:34","slug":"%e8%ae%a1%e7%ae%97%e6%9c%ba%e4%bd%93%e7%b3%bb%e7%bb%93%e6%9e%84-week-15-note","status":"publish","type":"post","link":"http:\/\/www.magicmipamipa.com\/?p=1117","title":{"rendered":"[\u8ba1\u7b97\u673a\u4f53\u7cfb\u7ed3\u6784] Week 15 Note"},"content":{"rendered":"<div>Reduce the miss penalty and miss rate via parallelism<\/div>\n<div>\u901a\u8fc7\u5e76\u884c\u51cf\u5c11\u5931\u914d\u635f\u5931\u548c\u5931\u914d\u7387<\/div>\n<div>\n<div>Nonblocking Caches to Reduce Stalls on Cache Misses \u975e\u963b\u585e\u7f13\u5b58\u4ee5\u51cf\u5c11\u7f13\u5b58\u672a\u547d\u4e2d\u65f6\u7684\u6682\u505c<\/div>\n<div><span>Hardware Prefetching of Instructions and data \u786c\u4ef6\u9884\u53d6<\/span><\/div>\n<div><span>Compiler-controlled prefetch \u7f16\u8bd1\u63a7\u5236\u7684\u9884\u53d6<\/span><\/div>\n<div>\u6309\u5757\u5b58\u50a8 \u6dfb\u52a0\u9884\u53d6\u6307\u4ee4 \u63d0\u524d\u5c06\u8981\u7528\u7684\u5757\u5148\u53d6\u51fa\u6765<\/div>\n<div><\/div>\n<div>Reduce the time to hit in the cache<\/div>\n<div>Small and Simple Caches \u5c0f\u800c\u7b80\u5355\u7684cache<\/div>\n<div>\n<div>Avoiding Address Translation during Indexing of the Cache \u907f\u514d\u5730\u5740\u8f6c\u6362<\/div>\n<div>TLB \u8f6c\u6362\u65c1\u8def\u7f13\u5b58 \u76f4\u63a5\u6620\u5c04\u865a\u5b9e\u5730\u5740<\/div>\n<div><span>Pipelined Cache Access\u00a0<\/span>\u5e76\u884c\u5904\u7406\u5730\u5740\u8f6c\u6362\u7b49\u884c\u4e3a<\/div>\n<div>Trace Caches \u8ddf\u8e2a\u7f13\u5b58<\/div>\n<\/div>\n<div><\/div>\n<div>\n<div>\n<div>Main Memory and Organizations for Improving Performance \u4e3b\u5b58\u7684\u7ec4\u6210\u6027\u80fd\u63d0\u9ad8<\/div>\n<div>Wider\u00a0<span>Main Memory \u4e3b\u5b58\u4f20\u8f93\u52a0\u5927 \u591a\u5b57\u4f20\u8f93<\/span><\/div>\n<div><span>Simple Interleaved Memory \u4ea4\u53c9\u4f20\u8f93<\/span><\/div>\n<div><span>Independent Memory Banks \u72ec\u7acb\u7684\u5185\u5b58\u5206\u533a<\/span><\/div>\n<div><\/div>\n<div>SRAM<\/div>\n<div>DRAM<\/div>\n<div>\u9759\u6001\u6d41\u6c34\u7ebf<\/div>\n<div>ROM \u53ea\u8bfb<\/div>\n<div>PROM \u53ef\u4ee5\u7f16\u7a0b<\/div>\n<div>EPROM \u53ef\u64e6\u9664\u53ef\u7f16\u7a0b<\/div>\n<div>EEPROM \u901a\u7535\u53ef\u64e6\u9664\u53ef\u7f16\u7a0b<\/div>\n<div>FLASH MEMORY<\/div>\n<\/div>\n<\/div>\n<div><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Reduce the miss penalty and miss rate via parallel [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[21,16],"tags":[],"_links":{"self":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts\/1117"}],"collection":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1117"}],"version-history":[{"count":3,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts\/1117\/revisions"}],"predecessor-version":[{"id":1123,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=\/wp\/v2\/posts\/1117\/revisions\/1123"}],"wp:attachment":[{"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1117"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1117"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.magicmipamipa.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1117"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}